Public summary
Join a leading semiconductor foundry's European design center in Munich as an IP Methodology and Design Flow Engineer. Work on advanced semiconductor technology focusing on cutting-edge nonvolatile memory solutions like MRAM and RRAM. Contribute to delivering state-of-the-art mixed-signal IP solutions by developing design flows, verification methodologies, timing closure methods, and automation scripts. Collaborate in a high-tech team supporting global customers in semiconductor logic chip manufacturing.
Location and work setup
- Location
- Munich
- Remote status
- On-site
- German requirement signal
- No German Required Detected
- Detected job language
- English
Responsibilities
Design, build, and support unified front-to-back design flows for mixed-signal IP development; define and enforce best practices for IP reuse and multi-node portability; establish robust Analog/Mixed-Signal verification methodologies including automated co-simulations; standardize behavioral model generation for system-level simulations; develop timing closure methodologies for analog-digital interfaces including static timing analysis and constraint generation; build and automate physical verification sign-off flows tailored for IP integration; create and maintain automation scripts in Python, Tcl, SKILL, and Perl to minimize errors and accelerate regression testing; define standard IP delivery packages and manage configuration and version control of design data and workspaces.
Qualifications
Master’s degree in Electrical or Computer Engineering or related field; 10+ years of experience in CAD, design methodology, or IP development for analog, digital, or mixed-signal circuits; strong hands-on experience with industry-standard EDA tools including Cadence Virtuoso, Synopsys Custom Compiler, Synopsys Design Compiler, Cadence Genus, and Innovus; expertise in Mixed-Signal verification using Cadence Xcelium/AMS Designer or Synopsys VCS/XA; proficient scripting skills in Tcl, Python, SKILL, and Shell scripting; deep understanding of IP packaging, process design kits, physical extraction techniques (PEX/EM/IR), and boundary timing constraints.