Public summary
Join a leading technology company as an Early Career Physical Design Engineer, contributing to the design and implementation of complex SoCs using state-of-the-art technology. You'll be responsible for block-level place-and-route, floor planning, clock and power distribution, static timing closure, power and noise analysis, layout verification, and documentation. This role requires strong knowledge of hierarchical design, static timing analysis, and experience with scripting languages such as Perl and TCL. Proficiency in English and excellent communication skills are essential.
Location and work setup
- Location
- Munich
- Remote status
- On-site
- German requirement signal
- No German Required Detected
- Detected job language
- English
Responsibilities
Own implementation of design partitions from netlist to final GDS in complex SoCs using advanced process technology. Perform block-level PnR, floor planning, clock and power distribution, static timing closure using commercial tools, power and noise analysis including EM/IR-Drop/Xtalk, and layout verification (DRC/LVS). Develop and validate clock network guidelines for high performance and low power. Identify and resolve design and flow issues, assist with documentation, guidelines, and specifications.
Qualifications
Understanding of hierarchical and top-down design approaches, timing and physical convergence. Knowledge of static timing analysis, clock/power distribution and analysis, RC extraction and correlation. Experience with SoC design practices including multiple voltage and clock domains, mixed-signal IP and I/O integration. Scripting skills in Perl, TCL, and/or Make. Fluent English communication skills. Preferred experience with Place & Route tools such as Synopsys or Cadence.