Public summary
Join a leading semiconductor design center in Munich, Germany, as a Digital Design Engineer. Contribute to cutting-edge embedded non-volatile memory IP development, including MRAM and RRAM technologies. Work with advanced RTL design, verification, and EDA tools to deliver state-of-the-art semiconductor products impacting global technology markets. Ideal candidates hold a Master's degree in Electrical Engineering and possess extensive experience in memory circuit and logic design.
Location and work setup
- Location
- Munich
- Remote status
- On-site
- German requirement signal
- No German Required Detected
- Detected job language
- English
Responsibilities
Define and document micro-architecture of RTL designs based on requirements; implement micro-architecture in synthesizable Verilog or SystemVerilog; support RTL to GDS flow including design constraints and implementation feasibility; utilize linting tools; collaborate with place & route teams for synthesis and implementation; perform logic synthesis, logic equivalency checking, and static timing analysis; develop and execute verification plans using Verilog/SystemVerilog and UVM; use industry-standard EDA tools such as Synopsys, Cadence, or Mentor Graphics; debug and resolve design issues including timing, power, and area optimization; collaborate with architects and product teams to assess and generate new ideas; optionally, contribute to flow automation and methodology improvements via scripting or AI tool evaluation.
Qualifications
Master's degree or higher in Electrical Engineering or related field; over 5 years of experience in non-volatile memory circuit or logic design (flash memory, RRAM, MRAM, PCRAM); familiarity with EDA tools and digital/custom design methodologies for non-volatile memory; strong skills in Verilog/SystemVerilog, RTL design, verification, and logic synthesis.