Public summary
Join a leading semiconductor design center in Munich as a Design for Test (DFT) Engineer. In this role, you will lead and develop test strategies for complex SoC projects, working with cutting-edge semiconductor technology including nonvolatile memory solutions. You will collaborate closely with synthesis, physical design teams, and participate in silicon bring-up and diagnostics to ensure high quality chip production.
Location and work setup
- Location
- Munich
- Remote status
- On-site
- German requirement signal
- No German Required Detected
- Detected job language
- English
Responsibilities
Define and lead DFT strategy and architecture for complex SoCs. Mentor and guide DFT engineers throughout the project lifecycle. Design and implement DFT flows using Synopsys and Siemens Tessent toolsets. Serve as the in-house expert on iJTAG integration, architecting hierarchical iJTAG networks. Implement scan insertion, MBIST, LBIST, and analog macro test structures. Generate and validate ATPG patterns and perform extensive pre-silicon DFT verification with gate-level simulations and timing analysis. Collaborate with synthesis and physical design teams to resolve timing, routing, and power issues relating to DFT. Lead silicon bring-up, automatic test equipment deployment, and debugging to diagnose yield issues and silicon failures.
Qualifications
Master's degree or higher in Electrical Engineering or related field. Minimum 5 years hands-on experience with DFT and test flow for large, complex SoCs. Strong knowledge of DFT methods including JTAG, ATPG, yield learning, logic diagnosis, scan compression, IEEE 1500 standard, and MBIST. Proficient in Synopsys DFT Compiler, Tetramax, VCS; experience with Tessent and Modus/Encounter tools a plus. Strong programming skills in Python, TCL, and shell scripting are required.